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586
NS9750 Hardware Reference
Panel clock divider restrictions
The data path latency forces some restrictions on the usable minimum values for the
panel clock divider in STN modes:
Single panel color mode: PCD = 1 (CLCP = CLCDCLK/3)
Dual panel color mode: PCD = 4 (CLCP = CLCDCLK/6)
Single panel mono 4-bit interface mode: PCD = 2 (CLCP = CLCDCLK/4)
Dual panel mono 4-bit interface mode: PCD = 6 (CLCP = CLCDCLK/8)
Single panel mono 8-bit interface mode: PCD = 6 (CLCP = CLCDCLK/8)
Dual panel mono 8-bit interface mode: PCD = 14 (CLCP = CLCDCLK/16)
D04:00 R/W PCD 0x00 Panel clock divisor
Derives the LCD panel clock frequency
CLCP from
the CLCDCLK frequency:
CLCP = CLCDCLK/(PCD+2)
For mono STN displays with a 4- or 8-bit
interface, the panel clock is a factor of four and
eight down on the actual individual pixel clock
rate.
For color STN displays, 2 2/3 pixels are output
per CLCP cycle, resulting in a panel clock of
0.375 times.
For TFT displays, the pixel clock divider can be
bypassed by setting the LCDTiming2 BCD bit
(D26).
See "Panel clock divider restrictions" on page 586 for
more information.
Bits Access Mnemonic Reset Description
Table 353: LCDTiming2 register