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Ethernet Control and Status registers
376
NS9750 Hardware Reference
Transmit total collision packet counter (A060 070C)
Incremented by the number of collisions experienced during the transmission of a
frame.
Note:
This register does not include collisions that result in an excessive
collision count or late collisions.
Transmit jabber frame counter (A060 0718)
Incremented for each oversized transmitted frame with an incorrect FCS value.
Transmit FCS error counter (A060 071C)
Incremented for every valid-sized packet with an incorrect FCS value.
Transmit oversize frame counter (A060 0724)
Incremented for each transmitted frame that exceeds 1518 bytes (NON_VLAN) or 1522
bytes
(VLAN) and contains a valid FCS.
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TNCL
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TJBR
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TFCS
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TOVR