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191
Memory Controller
Table 124 shows the outputs from the memory controller and the corresponding
inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects).
11 13 2
0 0 12 **
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 12 12
12 12 25 -
11 11 24 -
10 10/AP 23 AP
9 9 22 10
88 21 9
77 20 8
66 19 7
55 18 6
44 17 5
33 16 4
22 15 3
11 14 2
0 0 13 **
Table 124: Address mapping for 256M SDRAM (32Mx8, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 123: Address mapping for 256M SDRAM (16Mx16, RBC)