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195
Memory Controller
Table 129 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
99 19 -
88 18 9
77 17 8
66 16 7
55 15 6
44 14 5
33 13 4
22 12 3
11 11 2
0 0 10 **
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 21 21
13 BA0 22 22
12---
11 11 20 -
10 10/AP 19 AP
99 18 -
88 17 -
77 16 8
66 15 7
55 14 6
Table 129: Address mapping for 64M SDRAM (4Mx16, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 128: Address mapping for 16M SDRAM (2Mx8, BRC)