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685
IEEE 1284 Peripheral Controller
D11 R FCFR 0x0 Forward command FIFO ready
(FwCmdFifoReady)
Asserted if forward command in FIFO is enabled to move
data. Determined by FwCmdReadyThreshold (in the
IEEE 1284 General Configuration register).
D10:08 N/A Reserved N/A N/A
D07:06 R FDFDR 0x0 Forward data FIFO depth remain
(FwDatFifoDepthRemain)
00 4 bytes
01 1 byte
10 2 bytes
11 3 bytes
Determines how many bytes are valid in the current
forward data FIFO entry.
The current value in the field is not valid if the FIFO is
empty.
D05 R FDFE 0x1 Forward data FIFO empty
(FwDatFifoEmpty)
0 FIFO is not empty
1FIFO is empty
D04 R FDFAE 0x0 Forward data FIFO almost empty
(FwDatFifoAlmostEmpty)
0 FIFO has more than 1–4 bytes
1 FIFO has only one 1–4 byte entry
This field is not valid if the FIFO is empty.
D03 R FDFR 0x0 Forward data FIFO ready
(FwDatFifoReady)
Asserted if forward data in FIFO is enabled to move data.
Determined by FwDatReadyThreshold (in the IEEE 1284
General Configuration register).
D02 R RFF 0x0 Reverse FIFO full (RvFifoFull)
0 FIFO is not full
1 FIFO is full
Bits Access Mnemonic Reset Description
Table 393: FIFO Status register