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System control processor (CP15) registers
72
NS9750 Hardware Reference
Specific loading of addresses into a cache-way
The procedure to lock down code and data into way i of cache, with N ways, using
format C, makes it impossible to allocate to any cache way other than the target
cache way:
1 Be sure that no processor exceptions can occur during the execution of this
procedure; for example, disable interrupts. If this is not possible, all code and
data used by any exception handlers must be treated as code and data as in
Steps 2 and 3.
2 If an ICache way is being locked down, be sure that all the code executed by the
lockdown procedure is in an uncachable area of memory or in an already locked
cache way.
3 If a DCache way is being locked down, be sure that all data used by the lockdown
procedure is in an uncachable area of memory or is in an already locked cache
way.
4 Ensure that the data/instructions that are to be locked down are in a cachable
area of memory.
5 Be sure that the data/instructions that are to be locked down are not already in
the cache. Use the Cache Operations register (R7) clean and/or invalidate
functions to ensure this.
6 Write these settings to the Cache Lockdown register (R9), to enable allocation to
the target cache way:
CRm = 0
Set L == 0 for bit i
Set L == 1 for all other bits
7 For each of the cache lines to be locked down in cache way i:
– If a DCache is being locked down, use an LDR instruction to load a word
from the memory cache line to ensure that the memory cache line is loaded
into the cache.
– If an ICache is being locked down, use the Cache Operations register (R7)
MCR prefetch ICache line (<CRm>==c13, <opcode2>==1) to fetch the memory
cache line into the cache.
8 Write <CRm>==0 to Cache Lockdown register (R9), setting L==1 for bit i and
restoring all other bits to the values they had before the lockdown routine was
started.