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SPI-EEPROM boot logic
484
NS9750 Hardware Reference
SPI-EEPROM boot logic
SPI-EEPROM boot logic is enabled by strapping off the boot_cfg pins to the boot from
SDRAM
setting in the Miscellaneous System Configuration and Status register.
Table 291 shows the related boot settings.
When enabled, the boot logic copies the contents of an SPI-EEPROM to system
memory, allowing you to boot from a low-cost serial memory. The boot logic works by
interfacing to SER port B using the BBus — performing the transactions required to
copy the boot code from SPI-EEPROM to external memory.
Important
SPI-EEPROM must be connected to SER port B; the boot logic does not
communicate with any other SER port.
The endianness of the image in SPI must match the endianness of the
system.
In big endian mode, the boot image must be loaded as described in these
steps:
1 The entire boot image must be byte lane swapped before loading it
into the SPI boot device. Given a word of data composed of DCBA, byte
lane swapping transposes the bytes so the word looks like ABCD.
2 The image must only be loaded into the SPI boot device using the BBus
DMA controller. If the CPU directly loads the image into the SPI boot
device, an incorrect image is stored in the device.
boot_cfg [1:0] Description
00 Boot from 8-bit ROM or flash
01 Boot from 16-bit ROM or flash
10 Boot from 32-bit ROM or flash
11 Boot from SDRAM using SPI-EEPROM
Table 291: NS9750 boot configuration