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Pinout and signal descriptions
20
NS9750 Hardware Reference
H2 clk_en[3] 8 O SDRAM clock enable
A10 clk_out[0] 8 O SDRAM reference clock. Connect to clk_in[0]
using series termination.
A9 clk_out[1] 8 O SDRAM clock
A5 clk_out[2] 8 O SDRAM clock
A4 clk_out[3] 8 O SDRAM clock
G26 data[0] 8 I/O Data bus signal
H24 data[1] 8 I/O Data bus signal
G25 data[2] 8 I/O Data bus signal
F26 data[3] 8 I/O Data bus signal
G24 data[4] 8 I/O Data bus signal
F25 data[5] 8 I/O Data bus signal
E26 data[6] 8 I/O Data bus signal
F24 data[7] 8 I/O Data bus signal
E25 data[8] 8 I/O Data bus signal
D26 data[9] 8 I/O Data bus signal
F23 data[10] 8 I/O Data bus signal
E24 data[11] 8 I/O Data bus signal
D25 data[12] 8 I/O Data bus signal
C26 data[13] 8 I/O Data bus signal
E23 data[14] 8 I/O Data bus signal
D24 data[15] 8 I/O Data bus signal
C25 data[16] 8 I/O Data bus signal
B26 data[17] 8 I/O Data bus signal
D22 data[18] 8 I/O Data bus signal
C23 data[19] 8 I/O Data bus signal
B24 data[20] 8 I/O Data bus signal
Pin # Signal Name U/D
OD
(mA)
I/O Description
Table 3: System Memory interface pinout