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Static memory controller
148
NS9750 Hardware Reference
Table 77 provides the timing parameters. Table 78 describes the transactions for
Figure 55.
Figure 55: Read followed by a write (all 0 wait state) with two turnaround cycles
ADDROUT
DATAIN
OEOUT_n
D(A)
DATAOUT
D(B)
WEOUT_n
DATAEN_n
CSTCSOUT_n
B
A
0
clk_out
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Timing parameters Value
WAITRD 0
WAITOEN 0
WAITPAGE N/A
WAITWR 0
WAITWEN 0
WAITTURN 2
Table 77: Static memory timing parameters
Cycle Description
T0 AHB address provided to memory controller.
T0-T1 AHB transaction processing.
T1-T4 Arbitration of AHB memory ports.
Table 78: Read followed by a write (all 0 wait state) with two turnaround cycles