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recommended operating conditions 788
Reduced Media Independent Interface.
See
RMII.
register hash tables
366
regular timer 263
relinquishing the bus 257
reserved pins 45
reset and edge sensitive input timing
requirements
792
Reset and hardware strapping timing 835
Reset and Sleep Control register 295
reset function
boot sequence
11
master reset 10
RESET DONE as input 11
RESET DONE as output 11
reset values 204
resets, Ethernet 332
Reverse FIFO Write register 687
Reverse FIFO Write Register - Last 687
RMII 315
root hub, USB 752
RX A Buffer Descriptor Pointer Offset
register
391
RX A Buffer Descriptor Pointer
register
383
RX B Buffer Descriptor Pointer Offset
register
392
RX B Buffer Descriptor Pointer
retgister
383
RX C Buffer Descriptor Pointer Offset
register
393
RX C Buffer Descriptor Pointer
register
384
RX D Buffer Descriptor Pointer Offset
register
393
RX D Buffer Descriptor Pointer
register
384
RX Free Buffer register 395
S
sample hash table code 397
-
401
scan_en_n truth/termination table 28
SDRAM boot algorithm 488
-
489
self-refresh mode 118
Serial Channel B/A/C/D Bit-rate
register
624, 660
Serial Channel B/A/C/D Control Register
A
611, 652
Serial Channel B/A/C/D Control Register
B
614, 655
Serial Channel B/A/C/D FIFO Data
register
629, 665
Serial Channel B/A/C/D Flow Control
Force register
638
Serial Channel B/A/C/D Flow Control
register
636
Serial Channel B/A/C/D Receive Buffer
GAP Timer register
630
Serial Channel B/A/C/D Receive Character
GAP Timer register
632
Serial Channel B/A/C/D Receive Match
MASK register
635
Serial Channel B/A/C/D Receive Match
register
634
Serial Channel B/A/C/D Status Register
A
617, 657
serial controller
port features
4
UART features 4
serial controller, SPI 643
-
666
bit-rate generator 645
features 644
FIFO management 647
-
650
receive FIFO interface 648
Serial Channel B/A/C/D Bit-rate
register
660
Serial Channel B/A/C/D Control
Register A
652