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System Control Module features
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NS9750 Hardware Reference
System Control Module features
The System Control Module uses the following to configure and maintain NS9750
system operations:
AHB arbiter system
System-level address decoding
18 programmable timers
– Watchdog timer
– Bus monitor timer for the system bus (a second bus monitor timer, for
peripheral devices, is discussed in the BBus Bridge chapter)
– 16 general purpose timers/counters
Interrupt controller
Multiple configuration and status registers
System Sleep/Wake-up processor
Bus interconnection
The AMBA AHB bus protocol uses a central multiplexor interconnection scheme. All
bus masters generate the address and control signals that indicate the transfer that
the bus masters want to perform. The arbiter determines which master has its
address and control signals routed to all slaves. A central decoder is required to
control the read data and response multiplexor, which selects the appropriate signals
from the slave that is involved in the transfer.
System bus arbiter
The bus arbitration mechanism ensures that only one bus master has access to the
system bus at any time. If you are using a system in which bus bandwidth allocation is
critical, you must be sure that your worst-case bus bandwidth allocation goals can be