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Serial Control Module: UART
D05 R DSRI 0 Change in DSR
Indicates a state change in the EIA data set ready signal.
A 1 indicates that a state change has occurred. This field is
asserted only when the corresponding IE bit — RIC field,
D[05] — is set to 1 in Serial Channel Control Register A.
D04 R CTSI 0 Change in CTS
Indicates a state change in the EIA clear-to-send signal.
A 1 indicates that a state change has occurred. This field is
asserted only when the corresponding IE bit — TIC field,
D[04] — is set to 1 in Serial Channel Control Register A.
D03 R TRDY 0 Transmit register empty
Indicates that data can be written to the FIFO Data
register. TRDY typically is used only in interrupt-driven
applications; this field is not used for DMA operation. The
TRDY status condition can be programmed to generate an
interrupt by setting the corresponding IE bit in Serial
Channel Control Register A.
D02 R THALF 0 Transmit FIFO half empty
Indicates that the transmit data FIFO contains room for at
least 16 bytes. THALF typically is used only in interrupt-
driven applications; this field is not used for DMA
operation.
The THALF status condition can be programmed to
generate an interrupt by setting the corresponding IE bit in
Serial Channel Control Register A.
D01 R Not used N/A Must be written to 0.
D00 R TEMPTY 0 Transmit FIFO empty
Indicates that the transmit data FIFO currently is empty.
TEMPTY simply reports the status of the FIFO; this bit
does not indicate that the character currently in the
Transmit Shift register has been transmitted.
Bits Access Mnemonic Reset Description
Table 369: Serial Channel B/A/C/D Status Register A