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35
NS9750 Pinout
AE17 gpio[4]
1
U 2 I/O 00 Ser port B DTR
01 1284 busy (peripheral-driven)
02 DMA ch 1 done
03 GPIO 4
AF17 gpio[5] U 2 I/O 00 Ser port B DSR
01 1284 PError (peripheral-driven)
02 DMA ch 1 read enable
03 GPIO 5
AD16 gpio[6] U 2 I/O 00 Ser port B RI / SPI port B clk
01 1284 nFault (peripheral-driven)
3
02 Timer 7 (duplicate)
03 GPIO 6
AE16 gpio[7] U 2 I/O 00 Ser port B DCD / SPI port B enable
01 DMA ch 1 read enable (duplicate)
02 Ext IRQ 1
03 GPIO 7
AD15 gpio[8]
1
U 2 I/O 00 Ser port A TxData / SPI port A dout
01 Reserved
02 Reserved
03 GPIO 8
AE15 gpio[9] U 2 I/O 00 Ser port A RxData / SPI port A din
01 Reserved
02 Timer 8 (duplicate)
03 GPIO 9
AF15 gpio[10]
1
U 2 I/O 00 Ser port A RTS
01 Reserved
02 Reserved
03 GPIO 10
AD14 gpio[11] U 2 I/O 00 Ser port A CTS
01 Ext IRQ2 (duplicate)
02 Timer 0 (duplicate)
03 GPIO 11
Pin #
Signal
name
U/D
OD
(mA)
I/O Description (4 options: 00, 01, 02, 03)
Table 10: GPIO MUX pinout