Filter
Top Products
www.digiembedded.com
233
Memory Controller
Note:
Synchronous burst mode memory devices are not supported.
D03 R/W PM Page mode
0 Disabled (reset on
reset_n)
1 Async page mode enabled (page length four)
In page mode, the memory controller can burst up to four external
accesses. Devices with asynchronous page mode burst four or higher
are supported.
Asynchronous page mode burst two devices are not supported and
must be accessed normally.
D02 N/A Reserved N/A (do not modify)
D01:00 R/W MW Memory width
00 8 bit (reset value for chip select 0, 2, and 3 on
reset_n)
01 16 bit
10 32 bit
11 Reserved
The value of the chip select 1 memory width field on power-on reset
(
reset_n) is determined by the boot_strap[4:3] signal. This value can be
overridden by software. This field is not affected by AHB reset
(
HRESETn).
Note: For chip select 1, the value of the
boot_strap[4:3] signal is
reflected in this field. When programmed, this register
reflects the last value written into it.
Bits Access Mnemonic Description
Table 159: Static Memory Configuration 0–3 registers