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maximum power dissipation 789
Media Independent Interface. See MII.
memory controller
115
-
240
access sequencing and memory width,
dynamic memory
controller
162
access sequencing and memory width,
static memory controller
123
address connectivity 150
address mapping, dynamic memory
controller
163
-
201
bootstrap signals 119
bootstrap signals, memory
controller
119
bus turnaround 143
-
148
byte lane control 149
byte lane control and databus
steering
162
Configuration register 207
configuration, SPI-EEPROM 486
Control register 205
Dynamic Memory Active Bank A to
Active Bank B Time
register
222
Dynamic Memory Active to Active
Command Period register
219
Dynamic Memory Active to Precharge
Command Period register
214
Dynamic Memory Auto Refresh Period
register
220
Dynamic Memory Configuration 0-3
registers
225
address mapping 226
Dynamic Memory Control register 208
dynamic memory controller 162
-
201
Dynamic Memory Data-in to Active
Command Time register
217
Dynamic Memory Exit Self-refresh
register
221
Dynamic Memory Last Data Out to
Active Time register
216
Dynamic Memory Load Mode register
to Active Command Time
register
223
Dynamic Memory Precharge Command
Period register
213
Dynamic Memory RAS and CAS Delay 0-
3 registers
229
Dynamic Memory Read Configuration
register
212
Dynamic Memory Refresh Timer
register
210
Dynamic Memory Self-refresh Exit
Timer register
215
Dynamic Memory Write Recovery Time
register
218
extended wait transfers 122
features 116
low-power operation 118
memory map 118
memory mapped peripherals 123
memory timing diagrams 795
-
812
register addresses 202
registers 202
-
239
Static Memory Configuration 0-3
registers
230
static memory controller 121
-
162
static memory controller
configurations
121
static memory controller
initialization
123
-
148
Static Memory Extended Wait
register
224
Static Memory Output Enable Delay 0-
3 registers
235
Static Memory Page Mode Read Delay
0-3 registers
237
static memory read control 124
-
136
Static Memory Read Delay 0-3
registers
236