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About the PCI-to-AHB Bridge
406
NS9750 Hardware Reference
being sent back to the PCI bus. The AHB master interface supports both single and
burst transactions.
AHB slave/target interface
The AHB slave/target interface block controls the AHB target access to the bridge,
and is used for reads and writes to the PCI bus that are initiated on the AHB bus. The
requests are transferred to the PCI master interface. Writes are posted in the dual
64-byte AHB target write buffer and then transferred to the dual 64-byte PCI master
write buffer. Reads are delayed through the AHB SPLIT transaction protocol. Read
data is stored in the 64-byte PCI master read buffer. The AHB slave/target interface
supports both single and burst transactions.
The AHB slave provides the AHB interface to the PCI/Bridge configuration registers
(see page 411), using the
CONFIG_ADDR and CONFIG_DATA memory spaces.
PCI target interface
The PCI target interface block controls the PCI bus access to the AHB bus, and is used
for reads and writes that are initiated on the PCI bus by an external PCI bus master.
The requests are transferred to the AHB master interface. Writes are posted in the
dual 64-byte PCI target write buffer. The PCI target interface supports both single
and burst transactions.
PCI master interface
The PCI master interface block controls the bridge’s access to the PCI bus as a master,
and is used for reads and writes to the PCI bus that are initiated on the AHB bus. The
PCI master interfaces to the AHB slave/target interface, and receives its requests
from the AHB target interface. The PCI master has both a 64-byte read buffer and a
dual
64-byte write buffer. Both single and burst transactions are supported.
PCI/bridge configuration and status registers
The PCI/bridge configuration and status registers block contains standard PCI
configuration and status registers. All registers can be accessed using the PCI and AHB
buses (see "Configuration registers," beginning on page 411).