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209
Memory Controller
The Dynamic Memory Control register controls dynamic memory operation. The
control bits can be changed during normal operation.
Register bit assignment
Bits Access Mnemonic Description
D31:15 N/A Reserved N/A (do not modify)
D14 R/W nRP Sync/Flash reset/power down signal (
dy_pwr_n)
0
dy_pwr_n signal low (reset value on reset_n)
1Set
dy_pwr_n signal high
D13 R/W Not used Low-power SDRAM deep-sleep mode
0 Normal operation (reset value on reset_n)
1 Enter deep power down mode
D12:09 N/A Reserved N/A (do not modify)
D08:07 R/W SDRAMInit SDRAM initialization
00 Issue
SDRAM NORMAL operation command (reset value on
reset_n)
01 Issue
SDRAM MODE command
10 Issue SDRAM PALL (precharge all) command
11 Issue
SDRAM NOP (no operation) command
D06 N/A Reserved N/A (do not modify)
D05 R/W Not used Must write 0.
D04:03 N/A Reserved N/A (do not modify)
Table 141: Dynamic Memory Control register
CE
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
SDRAMInit ReservedRsvd nRP
Not
used
Reserved SR
Not
used
Rsvd
Not
used