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BBus Bridge
Register bit assignment
Bits Access Mnemonic Reset Description
D31 RW1TC NCIP 0 Normal completion interrupt pending
Set when a buffer descriptor has been closed.
A normal DMA completion occurs when the BLEN
count expires to 0 and the L bit in the Buffer descriptor
is set, or when the peripheral device signals completion.
D30 RW1TC ECIP 0 Error completion interrupt pending
Set when the DMA channel finds either a bad buffer
descriptor pointer or a bad data buffer pointer.
When ECIP is set, the DMA channel stops until
firmware clears the ECIP bit. The DMA channel does
not advance to the next buffer descriptor. When
firmware clears ECIP, the buffer descriptor is tried
again from where it left off.
You can use the CA bit in the DMA Channel 1/2 Control
register to abort the current buffer descriptor and go to
the next buffer descriptor.
D29 RW1TC NRIP 0 Buffer not ready interrupt pending
Set when the DMA channel finds a buffer descriptor
whose F bit is in the incorrect state. The F bit must be set
in order for the fetched buffer descriptor to be
considered valid. If the bit is not set, the descriptor is
considered invalid and the NRIP bit is set.
When NRIP is set, the DMA channel stops until
firmware clears the bit. The DMA channel does not
advance to the next buffer descriptor.
D28 RW1TC CAIP 0 Channel abort interrupt pending
Set when the DMA channel finds the CA bit set in the
DMA Channel 1/2 Control register.
When CAIP is set, the DMA channel stops until
firmware clears the bit. When CAIP is cleared, the
DMA channel automatically advances to the next buffer
descriptor.
The CA bit must be cleared, through firmware, before
CAIP is cleared. Failure to reset the CA bit causes the
subsequent buffer descriptor to abort.
Table 298: DMA Status and Interrupt Enable register bit definition