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Serial port control and status registers ............................................650
Serial Channel B/A/C/D Control Register A ................................652
Serial Channel B/A/C/D Control Register B ................................655
Serial Channel B/A/C/D Status Register A..................................657
Serial Channel B/A/C/D Bit-rate register...................................660
Serial Channel B/A/C/D FIFO Data register ................................665
Chapter 15:
IEEE 1284 Peripheral Controller ...................................669
Requirements ..........................................................................670
Overview ................................................................................670
Compatibility mode ............................................................671
Nibble mode .....................................................................672
Byte mode .......................................................................672
ECP mode ........................................................................673
Data and command FIFOs......................................................675
IEEE 1284 negotiation ..........................................................676
BBus slave and DMA interface .......................................................677
BBus slave and DMA interface register map ................................677
IEEE 1284 General Configuration register...................................679
Interrupt Status and Control register........................................681
FIFO Status register ............................................................684
Forward Command FIFO Read register ......................................686
Forward Data FIFO Read register.............................................687
Reverse FIFO Write register/Reverse FIFO Write Register — Last.......687
Forward Command DMA Control register ...................................689
Forward Data DMA Control register ..........................................690
Printer Data Pins register......................................................691
Port Status register, host......................................................692
Port Control register ...........................................................693
Port Status register, peripheral ..............................................694
Feature Control Register A ....................................................694
Feature Control Register B ....................................................695
Interrupt Enable register ......................................................695
Master Enable register .........................................................697
Extensibility Byte Requested by Host........................................698
Extended Control register .....................................................698
Interrupt Status register.......................................................699