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BBus Bridge Control and Status registers
494
NS9750 Hardware Reference
DMA Status and Interrupt Enable register
Address: A040 0008 / 0028
The DMA Status and Interrupt Enable register contains the DMA transfer status and
control information used for generating AHB DMA interrupt signals. The BBus bridge
contains a DMA Status and Interrupt Enable register for each DMA channel.
D16 R/W RST 0 Reset
Forces a reset of the DMA channel. Writing a 1 to this
field forces all fields in the DMA Channel 1/2 Control
register, except the INDEX field, to the reset state. The
INDEX field is written with a value specified on
signals
ahb_wdat[9:0]. This field always reads back a 0.
Writing a 1 to this field while the DMA channel is
operational results in unpredictable behavior.
D15:10 N/A Reserved N/A N/A
D09:00 R INDEX 0 Index value
Identifies the current byte offset pointer relative to the
buffer descriptor pointer. This field can be written
only when the RST field is being written to a 1.
Bit(s) Access Mnemonic Reset Description
Table 297: DMA Channel 1/2 Control register bit definition
13121110987654321015 14
BLEN
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
NRIP CAIP PCIP NCIE ECIE NRIE CAIE PCIE WRAP IDONE LAST FULLNCIP ECIP Not used