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PCI-to-AHB Bridge
PCI bus arbiter
The PCI bus arbiter (also referred to as PCI arbiter), although embedded in NS9750, is
not part of the PCI-to-AHB bridge protocol. See "PCI bus arbiter," beginning on page
418, for information about the PCI arbiter. The arbiter’s use is optional.
Cross-bridge transaction error handling
The PCI-to-AHB bridge supports several error-handling mechanisms. All mechanisms
can cause an interrupt to the system unless they are masked. Table 251 describes the
errors and resulting action.
PCI target error filtering
If the PCI target address or data parity checking logic finds an error during upstream
transactions, the transaction is not passed to the AHB master. In this situation, the
Error Action taken
PCI-to-AHB write
A write to the AHB bus does not complete due to
receipt of an AHB bus error
The AHBERR bit in the PCI Bridge Interrupt Status
register is set.
The AHB address is stored in the AHB Error Address
register in the bridge.
PCI-to-AHB read
A read to the AHB bus does not complete due to
receipt of an AHB bus error
The AHBERR bit in the PCI Bridge Interrupt Status
register is set.
The AHB address is stored in the AHB Error Address
register in the bridge.
A PCI target abort is issued to release the PCI bus
The SIGNALED TARGET ABORT bit in the PCI
Status register is set.
AHB-to-PCI write
A write to the PCI bus does not complete due to
receipt of a PCI bus error.
Bits [15:11] and [04] in the PCI Status register will
indicate the source of the PCI bus error.
The PCI address is stored in the PCI Error Address
register in the bridge.
AHB-to-PCI read
A read to the PCI bus does not complete due to
receipt of a PCI bus error.
Bits [15:11] and [04] in the PCI Status register will
indicate the source of the PCI bus error
The PCI address is stored in the PCI Error Address
register in the bridge.
Table 251: PCI-to-AHB error handling