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USB host block registers
762
NS9750 Hardware Reference
D07:05 N/A Not used N/A Always write to 0.
D04 R/W PRS 0b PortResetStatus (read)
0 Port reset signal is not active
1 Port reset signal is active
When this bit is set by a write to SetPortReset, port reset
signalling is asserted. When reset is completed, this bit is
cleared when PortResetStatusChange is set. This bit
cannot be set if CurrentConnectStatus is cleared.
SetPortReset (write)
The HCD sets the port reset signalling by writing a 1 to
this bit. Writing 0 has no effect. If CurrentConnectStatus
is cleared, this write does not set PortResetStatus; it sets
ConnectStatusChange, which tells the driver that it tried to
reset a disconnected port.
D03 R/W POCI 0b PortOverCurrentIndicator (read)
0 No overcurrent condition
1 Overcurrent condition found
Valid only when the root hub is configured such that
overcurrent conditions are reported on a per-port basis. If
per-port overcurrent reporting is not supported, this bit is
set to 0. If cleared, all power operations are normal for this
port. If set, an overcurrent condition exists on this port.
This bit always reflects the overcurrent input signal.
ClearSuspendedStatus (write)
The host controller driver writes a 1 to initiate a resume.
Writing 0 has no effect. A resume is initiated only if
PortSuspendStatus is set.
Bits Access Mnemonic Reset Description
Table 444: HcRhPortStatus[1] register