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Registers
238
NS9750 Hardware Reference
Static Memory Write Delay 0–3 registers
Address: A070 0214 / 0234 / 0254 / 0274
The Static Memory Write Delay 0–3 registers allow you to program the delay from the
chip select to the write access. These registers control the overall period for the
write cycle. It is recommended that these registers be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode.These
registers are not used if the extended wait bit is enabled in the related Static Memory
Configuration register (see page 230).
Register bit assignment
Bits Access Mnemonic Description
D31:05 N/A Reserved N/A (do not modify)
D04:00 R/W WTWR Write wait states (WAITWR)
00000–11110 (n+2) HCLK cycle write access time. The wait
state time for write accesses after the first read is
WAITWR (n+2) x t
HCLK
11111 332 HCLK cycle write access time (reset value on reset_n)
SRAM wait state time for write accesses after the first read.
Table 164: Static Memory Write Delay 0–3 registers
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WTWR