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Dynamic memory controller
174
NS9750 Hardware Reference
Table 103 shows the outputs from the memory controller and the corresponding
inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
66 20 8
55 19 7
44 18 6
33 17 5
22 16 4
11 15 3
00 14 2
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 13 13
13 BA0 14 14
12 12 27 -
11 11 26 12
10 10/AP 25 AP
9 9 24 11
8 8 23 10
77 22 9
66 21 8
55 20 7
44 19 6
33 18 5
22 17 4
Table 103: Address mapping for 512M SDRAM (64Mx8, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 102: Address mapping for 512M SDRAM (32Mx16, RBC)