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691
IEEE 1284 Peripheral Controller
b Forward data FIFO ready, which normally means the threshold has been
met, is asserted. This results in continuation of the currently active
DMA until the FIFO is empty.
c When the data in the FIFO, including the incomplete dwords in Step 1,
is output through DMA, the DMA is terminated.
Register bit assignment
Printer Data Pins register
Address: 9040 0100
Bits Access Mnemonic Reset Description
D31:16 R/W FwDatMaxBufSize 0x0 Forward data maximum buffer size
Maximum buffer size in bytes.
D15:00 R/W FwDatByteGapTimer 0x0 Forward data byte gap timeout
16-bit byte gap timer in BBus clock cycles.
Table 398: Forward Data DMA Control register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FwDatMaxBufSize
FwDatByteGapTimer
pd
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved