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Registers
222
NS9750 Hardware Reference
Dynamic Memory Active Bank A to Active Bank B Time register
Address: A070 0054
The Dynamic Memory Active Bank A to Active Bank B Time register allows you to
program the active bank A to active bank B latency, t
RRD
. It is recommended that this
register be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode. This value normally is found in SDRAM datasheets as t
RRD
.
Note:
The Dynamic Memory Active Bank A to Active Bank B Time register is used
for all four dynamic memory chip selects. The worst case value for all
chip selects must be programmed.
Register bit assignment
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W RRD Active bank A to Active bank B latency
0x0–0xE
n+1 clock cycles, where the delay is in CLK cycles
0xF
16 clock cycles (reset on reset_n)
Table 153: Dynamic Memory Active Bank A to Active Bank B Time register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved RRD