Filter
Top Products
www.digiembedded.com
799
Timing
SDRAM burst read (32-bit)
Figure 107: SDRAM burst read (32-bit) timing
Notes:
1 This is the bank and RAS address.
2 This is the CAS address.
prechg active read cas lat data-A data-B data-C data-D
M9
M8
M7
M6
M5
M11M4
M2
M1
Note-1 Note-2
clk_out<3:0>
data<31:0>
addr
data_mask<3:0>*
dy_cs_n<3:0>*
ras_n
cas_n
we_n