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177
Memory Controller
Table 107 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
11---
10 10/AP 20 AP
99 19 -
88 18 -
77 17 9
66 16 8
55 15 7
44 14 6
33 13 5
22 12 4
11 11 3
00 10 2
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 23 23
13 BA0 22 22
12---
11 11 21 -
10 10/AP 20 AP
99 19 -
88 18 -
77 17 9
Table 107: Address mapping for 64M SDRAM (4Mx16, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 106: Address mapping for 64M SDRAM (2Mx32, BRC)