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Working with the CPU
Figure 39 shows the set/way/word format for ARM926EJ-S caches.
Figure 39: ARM926EJ-S cache set/way/word format
In this figure:
A = log
2
associativity
For example, with a 4-way cache A = 2:
S = log
2
NSETS
Noncachable instruction fetches
The ARM926EJ-S processor performs speculative noncachable instruction fetches to
increase performance. Speculative instruction fetching is enabled at reset.
Note:
It is recommended that you use ICache rather than noncachable code,
when possible. Noncachable code previously has been used for operating
system boot loaders and for preventing cache pollution. ICache, however,
can be enabled without the MMU being enabled, and cache pollution can
be controlled using the cache lockdown register.
32 KB 8 256
64 KB 9 512
128 KB 10 1024
ARM926EJ-S S NSETS
Table 47: Values of S and NSETS
31 0
Way
31-A
32-A
S+5 S+4 5 4 2 1
SBZ SBZWord
Set select
(= Index)