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IEEE 1284 Peripheral Controller
Register bit assignment
Interrupt Status register
Address: 9040 012C
Interrupts are cleared when this register is read. These interrupts are needed by
software no matter which mode (DMA or CPU) is being used.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07 N/A Not used 0x0 Set to 1.
D06 R/W Enable reverse data transfers 0x0 0 Disable
1 Enable
D05:00 N/A Reserved N/A N/A
Table 407: ecr — Extended Control register
Bits Access Mnemonic Reset Description
D31:06 N/A Reserved N/A N/A
D05 R PSINT 0x0 Pin select interrupt
D04 R ECP Channel
Address
0x0 Channel address update detect interrupt
D03:02 N/A Reserved N/A N/A
D01 R NSDI 0x0 Negotiation start detect interrupt
Table 408: sti — Interrupt Status register
PSINT
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved
NSDI
ECPCh
Addr
TSDIReserved