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313
System Control Module
External Interrupt 0–3 Control register
Address: A090 0214 / 0218 / 021C / 0220
The External Interrupt Control registers control the behavior of external interrupts
0–3. The external interrupts are behind GPIO (see "GPIO MUX," beginning on page 34).
Register bit assignment
Bits Access Mnemonic Reset Description
D31:04 N/A Reserved N/A N/A
D03 R STS N/A Status
Status of the external signal before edge detect or level
conversion.
D02 R/W CLR 0x0 Clear
Write a 1, then a 0 to this bit to clear the interrupt
generated by the edge detect circuit.
D01 R/W PLTY 0x0 Polarity
0 If level-sensitive, the input source is active high.
If edge-sensitive, generate an interrupt on the rising
edge of the external interrupt.
1 If level-sensitive, the input source is active low. The
level is inverted before sending to the interrupt
controller.
If edge-sensitive, generate an interrupt on the falling
edge of the external interrupt.
D00 R/W LVEDG 0x0 Level edge
0 Level-sensitive interrupt
1 Edge-sensitive interrupt
Table 200: External Interrupt 0–3 Control register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved
STS CLR PLTY LVEDG