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SPI mode 646
individual mode definition 647
individual modes 646
See also serial controller, SPI.
SPI timing 827
-
830
SPI-EEPROM boot logic 484
-
489
ARM (memory) boot configuration 486
example 485
memory controller configuration 486
spike filter 552
SPLIT transfers 258
state machine 502
static (context) RAM 502
Static Memory Configuration 0-3
registers
230
static memory controller 121
-
162
configurations 121
extended wait transfers 122
initialization 123
-
148
memory mapped peripherals 123
write protection 122
static memory controller, access
sequencing and memory width
123
Static Memory Extended Wait register 224
static memory initialization 123
-
148
bus turnaround 143
-
148
static memory read control 124
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136
static memory write control 136
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143
wait state generation 123
Static Memory Output Enable Delay (0-3)
registers
235
Static Memory Page Mode Read Delay 0-3
registers
237
static memory read control 124
-
136
Static Memory Read Delay 0-3
registers
236
Static Memory Turn round Delay 0-3
registers
239
static memory write control 136
-
143
Static Memory Write Delay 0-3
registers
238
Static Memory Write Enable Delay 0-3
registers
234
Station Address Filter register 366
station address logic (SAL) 321
Station Address registers 364
statistics module 321
Statistics registers (Ethernet) 368
combined transmit and receive
statistics counters
368
receive statistics counters 369
transmit statistics counters 373
status bit, Ethernet 326, 328
status field 506
Status Receive Data register 549
Status register, memory 207
STN display panels 564
STN displays 565
synchronization logic 568
system address map 261
system boot
BBus bridge function
468
system bus 5
system bus arbiter 254
-
260
configuration examples 258
CPU arbiter, high-speed 255
CPU subsystem 255
locked bus sequence 257
main arbiter, high-speed 256
ownership 257
procedure 256
relinquishing the bus 257
SPLIT transfers 258
system clock 13
system clock generation, PLL 272
system configuration registers 276
-
313
register addresses 276