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BBus Bridge
transferring data in non-DMA mode do not contribute to the calculation. The worst
case AHB DMA response latency occurs when all of the BBus peripherals perform these
operations within several microseconds of each other:
Move the remaining data in or out of the data buffer.
Close the buffer descriptor.
Open a new buffer descriptor.
Begin processing the new data buffer. This can be two steps for a
transmitter.
Two AHB bandwidth calculations are defined here. The first scheme shows the worst
case, where the BBus is given one out of ten AHB timeslots. The second scheme shows
the best case, where the BBus is given one out of every four AHB timeslots.
Worst case:
AHB access = ((16 * 10 * 2) / 200 MHz) = 1.60us
This AHB access pattern looks like this:
Cpu, Erx, Cpu, Etx; Cpu, Lcd, Cpu, Pci; Cpu, BBus
Best case:
AHB access = ((16 * 4 * 2) / 200 MHz) = 0.64us
This AHB access pattern looks like this:
Cpu, Erx, Cpu, BBus; Cpu, Etx, Cpu, BBus; Cpu, Lcd, Cpu, BBus; Cpu, Pci; Cpu, BBus
Each receive channel contributes four AHB accesses to the calculation. Each transmit
channel contributes five AHB accesses to the calculation. The USB device (or USB
host) and IEEE 1284 are half-duplex-only peripherals, so only the transmit channel
needs to be accounted for.
Also take into account adjustment for AHB DMA channel overhead: two if one DMA
channel is in use and six if both DMA channels are in use. The worst case and best
case equations for two DMA channels work out as shown:
Worst case latency =
1.60us * ((#Receive * 4) + (#Transmit * 5) + 6)
Best case latency = 0.64us * ((#Receive * 4) + (#Transmit * 5) + 6)
In a fully loaded system with four UARTs, IEEE 1284, and USB, the worst case latency
is 83.2us and the best case latency is 33.28us.