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BBus Bridge Control and Status registers
492
NS9750 Hardware Reference
Register bit assignment
Bit(s) Access Mnemonic Reset Description
D31 R/W CE 0 Channel enable
Enables and disables DMA operations, as wanted.
Write a 1 to this field after a DMA channel has entered
the IDLE state for any reason, to initiate additional
DMA transfers.
D30 R/W CA 0 Channel abort
When set, causes the current DMA operation to
complete, then closes the buffer.
D29 R/W CG 0 Channel go
When set, causes the DMA channel to exit the IDLE
status and begin a DMA transfer.
Note: The CE field must also be set. This allows
software to initiate a memory-to-memory
DMA transfer. External peripheral signal
REQ is not used during memory-to-
memory DMA transfers.
D28:27 R/W SW 0 Source width
Defines the size of the source data bus. Used only for
peripheral to memory transfers.
00 8 bits
01 16 bits
10 32 bits
11 Undefined
D26:25 R/W DW 0 Destination width
Defines the size of the destination data bus. Used only
for memory to peripheral transfers.
00 8 bits
01 16 bits
10 32 bits
11 Undefined
Table 297: DMA Channel 1/2 Control register bit definition