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System control processor (CP15) registers
62
NS9750 Hardware Reference
Each two-bit field defines the access permissions for one of the 16 domains (D15–D0):
00 No access: Any access generates a domain fault
01 Client: Accesses are checked against the access permission bits in the section or page descriptor
10 Reserved: Currently behaves like no access mode (00)
11 Manager: Accesses are not checked against the access permission bits, so a permission fault
cannot be generated.
Use these instructions to access the Domain Access Control register:
MRC p15, 0, Rd, c3, c0, 0 ; read domain access permissions
MCR p15, 0, Rd, c3, c0, 0 ; write domain access permissions
R4 register
Accessing (reading or writing) this register causes UNPREDICTABLE behavior.
R5: Fault Status registers
Register R5 accesses the Fault Status registers (FSRs). The Fault Status registers
contain the source of the last instruction or data fault. The instruction-side FSR is
intended for debug purposes only.
The FSR is updated for alignment faults and for external aborts that occur while the
MMU is disabled. The FSR accessed is determined by the
opcode_2 value:
See "Memory Management Unit (MMU)," beginning on page 78, for the fault type
encoding.
Access the FSRs using these instructions:
MRC p15, 0, Rd, c5, c0, 0 ; read DFSR
MCR p15, 0, Rd, c5, c0, 0 ; write DFSR
MRC p15, 0, Rd, c5, c0, 1 ; read IFSR
MCR p15, 0, Rd, c5, c0, 1 ; write IFSR
opcode_2=0 Data Fault Status register (DFSR)
opcode_2=1 Instruction Fault Status register (IFSR)