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Dynamic memory controller
178
NS9750 Hardware Reference
Table 108 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
66 16 8
55 15 7
44 14 6
33 13 5
22 12 4
11 11 3
00 10 2
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 23 23
13 BA0 24 24
12---
11 11 22 -
10 10/AP 21 AP
99 20 -
8 8 19 10
77 18 9
66 17 8
55 16 7
44 15 6
33 14 5
22 13 4
Table 108: Address mapping for 64M SDRAM (8Mx8, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 107: Address mapping for 64M SDRAM (4Mx16, BRC)