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257
System Control Module
Ownership
Ownership of the data bus is delayed from ownership of the address/control bus.
When
hready indicates that a transfer is complete, the master that owns the address/
control bus can use the data bus — and continues to own that data bus — until the
transaction completes.
Note:
If a master is assigned more than one request/grant channel, these
channels need to be set and reset simultaneously to guarantee that a non-
requesting master will not occupy the system bus.
Locked bus sequence
The arbiter observes the
hlock_x signal from each master to allow guaranteed back-to-
back cycles, such as read-modified-write cycles. The arbiter ensures that no other
bus masters are granted the bus until the locked sequence has completed. To support
SPLIT or RETRY transfers in a locked sequence, the arbiter retains the bus master as
granted for an additional transfer to ensure that the last transfer in the locked
sequence completed successfully.
If the master is performing a locked transfer and the slave issues a split response, the
master continues to be granted the bus until the slave finishes the SPLIT response.
(This situation degrades AHB performance.)
Relinquishing the bus
When the current bus master relinquishes the bus, ownership is granted to the next
requester.
If there are no new requesters, ownership is granted to a dummy default
master. The default master must perform IDLE transfers to keep the arbiter
alive.
Bus parking must be maintained if other masters are waiting for SPLIT
transfers to complete.
If the bus is granted to a default master and continues to be in the IDLE
state longer than a specified period of time, an AHB bus arbiter timeout is
generated (see "Address decoding" on page 261). An AHB bus arbiter timeout
can be configured to interrupt the CPU or to reset the chip.