Filter
Top Products
PCI bus arbiter
430
NS9750 Hardware Reference
Register bit assignment
PCI Configuration 2 register
Address: A030 0018
The PCI Configuration 2 register contains the values that will be read from the PCI
Subsystem ID and PCI Subsystem Vendor ID registers.
Change these fields only during system initialization, when there is no PCI activity. In
a system where NS9750 is not the host, these fields must be programmed within 2
25
PCI clocks of
RST# being negated. This is the time allowed from RST# negated to the
first configuration cycle on the PCI bus.
Bits Access Mnemonic Reset Description
D31:08 R/W CLASS_CODE 0x060000 Class code value
Value to be inserted into PCI Class Code register.
Defaults to class code for a
host/PCI bridge (0x060000).
D07:00 R/W REVISION_ID 0x00 Revision ID value
Value to be inserted into the PCI Revision ID
register. Defaults to
0x00.
Table 265: PCI Configuration 1 register
CLASS_CODE
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
CLASS_CODE REVISION_ID
SUBSYSTEM_ID
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
SUBVENDOR_ID