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235
Memory Controller
Static Memory Output Enable Delay 0–3 registers
Address: A070 0208 / 0228 / 0248 / 0268
The Static Memory Output Enable Delay 0–3 registers allow you to program the delay
from the chip select or address change, whichever is later, to the output enable
assertion. The Static Memory Output Enable Delay register is used in conjunction with
the Static Memory Read Delay registers, to control the width of the output enable
signals. It is recommended that these registers be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode.
Register bit assignment
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W WOEN Wait output enable (WAITOEN)
0000 No delay (reset value on reset_n).
0001–1111 n cycle delay, where the delay is
WAITOEN x t
HCLK
Delay from chip select assertion to output enable.
Table 161: Static Memory Output Enable Delay 0–3 registers
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WOEN