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about 48
cache format 110
DSP 78
Jazelle (Java) 77
Memory Management Unit. See MMU.
system register addresses 51
ARM926EJ-S RISC processor 2
attributes, system control module 271
-
276
B
Back-to-Back Inter-Packet_Gap
register
354
bandwidth requirements 483
BBus
master and slave modules
472
BBus bridge 467
-
500
arbitration (masters and slaves) 472
arbitration and multiplexing 468
bandwidth requirements 483
BBus Bridge Interrupt Enable
register
499
BBus Bridge Interrupt Status
register
498
Buffer Descriptor Pointer register 491
Control and Status registers 490
-
500
control logic 469, 472
-
473
descriptor list processing 476
DMA accesses 471
DMA buffer descriptor 474
DMA Channel 1/2 Control register 491
DMA memory-to-peripheral
transfers
471
DMA Peripheral Chip Select
register
496
DMA peripheral-to-memory
transfers
471
DMA Status and Interrupt Enable
register
494
functions 468
interrupt aggregation 483
main function 467
peripheral address map 473
register addresses 490
SDRAM boot algorithm 488
-
489
SPI-EEPROM boot logic 484
-
489
SPI-EEPROM boot logic, memory
controller configuration
486
system boot engine 468
two-channel DMA controller 468,
474
-
483
BBus bridge arbitration
cycles
473
masters and slaves 472
BBus Bridge Control and Status
registers
490
-
500
BBus Bridge Interrupt Enable register 499
BBus Bridge Interrupt Status register 498
BBus DMA controller 501
-
519
about the controllers 502
controller block 503
DMA buffer descriptor 504
-
508
DMA Buffer Descriptor Pointer
register
512
DMA channel assignments 509
-
510
DMA context memory 503
DMA Control register 514
DMA Status/Interrupt Enable
register
516
DMA transfer status 506
-
508
fly-by DMA transfers 502
fly-by mode 502
register addresses 511
BBus DMA Interrupt Enable register 537
BBus DMA Interrupt Status register 536
BBus Monitor register 535