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LCD Controller
D16 R/W WATERMARK 0x0 LCD DMA FIFO watermark level
0 LCD controller requests AHB bus when either
of the DMA FIFOs have at least four empty
locations.
1 LCD controller requests AHB bus when either
of the DMA FIFOs have at least eight empty
locations. (Use this setting for optimum bus
bandwidth.)
D15:14 N/A Reserved N/A N/A
D13:12 R/W LcdVComp 0x0 Generate vertical compare interrupt (VCOMP; see
"LCDStatus register" on page 593) at one of the
following:
00 Start of vertical synchronization
01 Start of back porch
10 Start of active video
11 Start of front porch
D11 R/W LcdPwr 0x0 LCD power enable
0 Power not gated through to LCD panel and
CLD[23:0] signals disabled (held low).
1 Power gated through to LCD panel and
CLD[23:0] signals enabled (active).
See "LCD power up and power down sequence
support" on page 563 for additional information.
D10 R/W BEPO 0x0 Big endian pixel ordering within a byte
0 Little endian pixel ordering within a byte.
1 Big endian pixel ordering within a byte.
The BEPO bit selects between Little and Big endian
pixel packing for 1, 2, and 4 bpp display modes; the
bit has no effect on 8 or 16 bpp pixel formats.
See "Pixel serializer" on page 569 for additional
information.
D09 R/W BEBO 0x0 Big endian byte order
0 Little endian byte order
1 Big endian byte order
D08 R/W BGR 0x0 RGB or BGR format selection
0 RGB: Normal output
1 BGR: Red and blue swapped
Bits Access Mnemonic Reset Description
Table 358: LCDControl register