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Interrupt Status Raw ...........................................................152
Timer Interrupt Status register...............................................153
Software Watchdog Configuration register .................................153
Software Watchdog Timer register ..........................................155
Clock Configuration register ..................................................155
Reset and Sleep Control register .............................................157
Miscellaneous System Configuration and Status register .................158
PLL Configuration register.....................................................161
Active Interrupt Level Status register .......................................163
Timer 0–15 Control registers ..................................................163
System Memory Chip Select 0 Dynamic Memory Base and Mask registers..
165
System Memory Chip Select 1 Dynamic Memory Base and Mask registers..
166
System Memory Chip Select 2 Dynamic Memory Base and Mask registers..
167
System Memory Chip Select 3 Dynamic Memory Base and Mask registers..
168
System Memory Chip Select 0 Static Memory Base and Mask registers.169
System Memory Chip Select 1 Static Memory Base and Mask registers.170
System Memory Chip Select 2 Static Memory Base and Mask registers.171
System Memory Chip Select 3 Static Memory Base and Mask registers.172
Gen ID register ..................................................................173
External Interrupt 0–3 Control register......................................175
Chapter 5:
Memory Controller .............................................................................177
Features.................................................................................178
System overview ................................................................179
Low-power operation ..........................................................180
Memory map.....................................................................180
Static memory controller.............................................................183
Write protection ................................................................184
Extended wait transfers .......................................................184
Memory mapped peripherals..................................................185
Static memory initialization ..................................................185
Byte lane control ...............................................................211
Address connectivity ...........................................................212
Byte lane control and databus steering .....................................216