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System Control Module
Example 1
Since the 20 Mbyte per master guarantee meets the requirements of all masters, the
AHB arbiter will be programmed as follows:
BRC0[31:24] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S
BRC0[23:16] = 8’b1_0_00_0001 channel enabled, 100%, Ethernet Rx
BRC0[15:8] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S
BRC0[7:0] = 8’b1_0_00_0010 channel enabled, 100% Ethernet Tx
BRC1[31:24] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S
BRC1[23:16] = 8’b1_0_00_0100 channel enabled, 100%, PCI
BRC1[15:8] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S
BRC1[7:0] = 8’b1_0_00_0101 channel enabled, 100%, BBus
BRC2[31:24] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S
BRC2[23:16] = 8’b1_0_00_0100 channel enabled, 100%, LCD
BRC2[15:8] = 8’b0_0_00_0000 channel disabled
BRC2[7:0] = 8’b0_0_00_0000 channel disabled
BRC3[31:24] = 8’b0_0_00_0000 channel disabled
BRC3[23:16] = 8’b0_0_00_0000 channel disabled
BRC3[15:8] = 8’b0_0_00_0000 channel disabled
BRC[7:0] = 8’b0_0_00_0000 channel disabled
Example 2
In this example, the LCD master needs more than 20 Mbytes and the other masters
need less than 20 Mbytes. These are the new requirements:
Ethernet Rx — 12.5 Mbytes
Ethernet Tx — 12.5 Mbytes
PCI — 16 Mbytes
BBus — 4 Mbytes
LCD — 25 Mbytes
Total — 70 Mbytes
This configuration is possible because the total bandwidth is less than the 100 Mbytes
available. The LCD master will be configured to have two arbiter slots, resulting in a
total of 6 masters.