Filter
Top Products
www.digiembedded.com
59
Working with the CPU
[15] L4 Determines whether the T is set when load instructions change
the PC.
0 Loads to PC set the T bit
1 Loads to PC do not set the T bit
[14] RR bit Replacement strategy for ICache and DCache
0 Random replacement
1 Round-robin replacement
[13] V bit Location of exception vectors
0 Normal exception vectors selected; address range=
0x0000
0000
to 0x0000 001C
1 High exception vectors selected; address range=0xFFFF
0000
to 0xFFFF 001C
Set to the value of VINITHI on reset.
[12] I bit ICache enable/disable
0 ICache disabled
1 ICache enabled
[11:10] N/A
SHOULD BE ZERO
[9] R bit ROM protection
Modifies the ROM protection system.
[8] S bit System protection
Modifies the MMU protection system. See "Memory
Management Unit (MMU)," beginning on page 78.
[7] B bit Endianness
0 Little endian operation
1 Big endian operation
Set to the value of
BIGENDINIT on reset.
[6:3] N/A Reserved. SHOULD BE ONE.
[2] C bit DCache enable/disable
0 Cache disabled
1 Cache enabled
[1] A bit Alignment fault enable/disable
0 Data address alignment fault checking disabled
1 Data address alignment fault checking enabled
Bits Name Function
Table 22: R1: Control register bit definition