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USB Device Endpoint FIFO Control and Data registers
780
NS9750 Hardware Reference
Register bit assignment
FIFO Packet Control registers
Address: 9010 3080 / 3084 / 3088 / 308C / 3090 / 3094 / 3098 / 309C / 30A0 / 30A4 / 30A8 / 30AC
/ 30B0
The FIFO Packet Control registers contain packet information for the device block
FIFOs. There are 13 of these registers in the USB module, one for each non-control
endpoint and the two required for the bidirectional control endpoint.
Bits Access Mnemonic Reset Description
D31:24 N/A Not used 0x00 Always read as 0x00.
D23 R/W ACK13 0 Generate an interrupt when ACK13 in FIFO Interrupt
Status 3 register is asserted.
D22 R/W NACK13 0 Generate an interrupt when NACK13 in FIFO Interrupt
Status 3 register is asserted.
D21 R/W ERROR13 0 Generate an interrupt when ERROR13 in FIFO Interrupt
Status 3 register is asserted.
D20:16 N/A Reserved N/A Not valid in DMA mode.
D15 R/W ACK12 0 Generate an interrupt when ACK12 in FIFO Interrupt
Status 3 register is asserted.
D14 R/W NACK12 0 Generate an interrupt when NACK12 in FIFO Interrupt
Status 3 register is asserted.
D13 R/W ERROR12 0 Generate an interrupt when ERROR12 in FIFO Interrupt
Status 3 register is asserted.
D12:08 N/A Reserved N/A Not valid in DMA mode.
D07 R/W ACK11 0 Generate an interrupt when ACK11 in FIFO Interrupt
Status 3 register is asserted,
D06 R/W NACK11 0 Generate an interrupt when NACK11 in FIFO Interrupt
Status 3 register is asserted.
D05 R/W ERROR11 0 Generate an interrupt when ERROR11 in FIFO Interrupt
Status 3 register is asserted.
D04:00 N/A Reserved N/A Not valid in DMA mode.
Table 457: FIFO Interrupt Enable 3 register