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BBus slave and DMA interface
686
NS9750 Hardware Reference
Forward Command FIFO Read register
Address: 9040 000C
Register bit assignment
D01 R RFAF 0x0 Reverse FIFO almost full (RvFifoAlmostFull)
0 FIFO can take more than 1–4 bytes
1 FIFO can take only one 1–4 byte entry
This field is not valid id the FIFO is full.
D00 R RFR 0x0 Reverse FIFO ready (RvFifoReady)
Asserted if reverse data out FIFO is enabled to move data.
Determined by RvDatReadyThreshold (in the IEEE 1284
General Configuration register).
Bits Access Mnemonic Reset Description
Table 393: FIFO Status register
Bits Access Mnemonic Reset Description
D31:00 R FwCmdFifoReadReg N/A Reads up to four bytes from the Forward
Command FIFO when in CPU mode. The CPU
must read the FIFO Status register (see
page 684) to determine how many bytes are
remaining before issuing the read.
Table 394: Forward Command FIFO Read register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FwCmdFifoReadReg
FwCmdFifoReadReg