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USB host block registers
760
NS9750 Hardware Reference
D18 R/W PSSC 0b PortSuspendStatusChange
0 Resume is not completed
1 Resume completed
Set when the full resume sequence has been completed.
This sequence includes the 20-s resume pulse, LS EOP,
and 3-ms resynchronization delay. The host controller
driver writes a 1 to clear this bit. Writing 0 has no effect.
This bit also is cleared when ResetStatusChange is set.
D17 R/W PESC 0b PortEnableStatusChange
0 No change in PortEnableStatus
1 Change in PortEnableStatus
Set when hardware events cause the PortEnableStatus bit
to be cleared. Changes from host controller driver writes
do not set this bit. The host controller driver writes a 1 to
clear this bit. Writing 0 has no effect.
D16 R/W CSC 0b ConnectStatusChange
0 No change in CurrentConnectStatus
1 Change in CurrentConnectStatus
Set when a connect or disconnect event occurs. The host
controller driver writes a 1 to clear this bit. Writing 0 has
no effect. If CurrentConnectStatus is cleared when a
SetPortReset, SetPortEnable, or SetPortSuspend write
occurs, this bit is set to force the driver to re-evaluate the
connection status, as these writes should not occur if the
port is disconnected.
Note: If the DeviceRemovable[NDP] bit is set, the
CSC bit is set only after a root hub reset, to tell
the system that the device is attached.
D15:10 N/A Not used N/A Always write to 0.
Bits Access Mnemonic Reset Description
Table 444: HcRhPortStatus[1] register