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USB Device Endpoint FIFO Control and Data registers
772
NS9750 Hardware Reference
Register bit assignment
Bits Access Mnemonic Reset Description
D31 RW1TC ACK6 0 Endpoint 4 acknowledge status. See Table 449, “USB
device endpoint status,” on page 770.
D30 RW1TC NACK6 0 Endpoint 4 negative acknowledge status. See Table 449,
“USB device endpoint status,” on page 770.
D29 RW1TC ERROR6 0 Endpoint 4 error status. See Table 449, “USB device
endpoint status,” on page 770.
D28:24 N/A Reserved N/A Not valid in DMA mode.
D23 RW1TC ACK5 0 Endpoint 3 acknowledge status. See Table 449, “USB
device endpoint status,” on page 770.
D22 RW1TC NACK5 0 Endpoint 3 negative acknowledge status. See Table 449,
“USB device endpoint status,” on page 770.
D21 RW1TC ERROR5 0 Endpoint 3 error status. See Table 449, “USB device
endpoint status,” on page 770.
D20:16 N/A Reserved N/A Not valid in DMA mode.
D15 RW1TC ACK4 0 Endpoint 2 acknowledge status. See Table 449, “USB
device endpoint status,” on page 770.
D14 RW1TC NACK4 0 Endpoint 2 negative acknowledge status. See Table 449,
“USB device endpoint status,” on page 770.
D13 RW1TC ERROR4 0 Endpoint 2 error status. See Table 449, “USB device
endpoint status,” on page 770.
D12:08 N/A Reserved N/A Not valid in DMA mode.
D07 RW1TC ACK3 0 Endpoint 1 acknowledge status. See Table 449, “USB
device endpoint status,” on page 770.
Table 451: FIFO Interrupt Status 1 register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
ERROR
4
Reserved
ACK4
NACK
4
Reserved
ACK3
NACK
3
ERROR
3
ACK6
NACK
6
ERROR
6
ERROR
5
NACK
5
ACK5
Reserved