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517
BBus DMA Controller
Register bit assignment
Bits Access Mnemonic Reset Description
D31 RW1TC NCIP 0 Normal completion interrupt pending
Set when a buffer descriptor is closed (for normal
conditions). An interrupt is generated when either the
NCIE (D24) bit is set or the IDONE (D18) bit is found
active in the current buffer descriptor.
A normal DMA channel completion occurs when the
BLEN count (15:00) expires to 0 or when a peripheral
device signals completion.
D30 RW1TC ECIP 0 Error completion interrupt pending
Set when the DMA channel encounters either a bad buffer
descriptor pointer or a bad data buffer pointer. An
interrupt is generated if the ECIE (D23) bit is set.
The DMA channel stops until the CE bit (in the DMA
Channel Control register) is written to a 1 by firmware.
The DMA channel does not advance to the next buffer
descriptor. When ECIP Is cleared by firmware, the buffer
descriptor is tried again from where it left off.
The CA bit in the appropriate DMA Channel Control
register can be used to abort the current buffer descriptor
and advance to the next buffer.
D29 RW1TC NRIP 0 Buffer not ready interrupt pending
Set when the DMA channel finds a buffer descriptor
whose F bit is in the incorrect state. An interrupt is
generated if the NRIE (D22) bit is set.
When NRIP is set, the DMA channel stops until firmware
writes a 1 to the CE field (in the DMA Channel Control
register). The DMA channel does not advance to the next
buffer descriptor.
Table 314: DMA Status/Interrupt Enable register bit definition