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System bus arbiter
258
NS9750 Hardware Reference
SPLIT transfers
A SPLIT transfer occurs when a slave is not ready to perform the transfer. The slave
splits, or masks, its master, taking away the master’s bus ownership and allowing
other masters to perform transactions until the slave has the appropriate resources
to perform its master’s transaction.
The bus arbiter supports SPLIT transfers. When a SPLIT response is issued by a slave,
the current master is masked for further bus requesting until a corresponding
hsplit_x[15:0] signal is issued by the slave indicating that the slave is ready to complete
the transfer. The arbiter uses the
hsplit_x[15:0] signals to unmask the corresponding
master, and treats the master as the highest-priority requester for the immediate
next round of arbitration. The master eventually is granted access to the bus to try
the transfer again.
Note:
The arbiter automatically blocks bus requests with addresses directed at a
“SPLITting” slave until that SPLIT transaction is completed.
Arbiter configuration examples
These examples show how to configure the AHB arbiter to guarantee bandwidth to a
given master. These are the conditions in this example:
5 AHB masters — Ethernet Rx, Ethernet Tx, PCI, BBus, and LCD.
Memory clock frequency — 100 MHz (this is the AHB clock frequency).
Average access time per 32-byte memory access — 16 clock cycles.
The ARM926EJ-S is guaranteed one-half the total memory bandwidth.
In these examples, the bandwidth for each master can be calculated using this
formula:
Bandwidth per master:
= [(100MHz/2) / (16 clock cycles per access x 5 masters)] x 32 bytes
= 20 Mbytes/master
The factor 100MHz/2 is given due to the ARM926EJ-S guarantee of one-half the total
memory bandwidth. If the ARM926EJ-S consumes less than the guaranteed memory
bandwidth, however, the unused bandwidth will be shared by the other masters.
Note:
The worst case scenario is that there are 100 Mbytes total to be split by
all 5 masters.